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Test bench file⚓

A test bench is a VHDL file that will only be used to test one or more components. Its VHDL description is not necessarily synthesizable, it is even rarely synthesizable. Indeed we often use non-synthesizable features such as wait and after

A test bench is a module that has no inputs/outputs, it only includes one or more components, drives their inputs and possibly monitors their outputs.

Test bench

Test bench
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- exemple de test bench

entity tb_Module is
end tb_Module;

architecture archi_tb_Module of tb_Module is

component Module is     -- module que l'on souhaite tester
    generic(
        G_GenericA  : integer;
        G_GenericB  : integer
    );
    port(
        I_Clock         : in  std_logic;
        I_Reset         : in  std_logic;
        I_Enable        : in  std_logic;
        I_Data          : in  std_logic_vector(G_GenericA-1 downto 0);
        I_Address       : in  std_logic_vector(G_GenericB-1 downto 0);
        O_Ready         : out std_logic;
        O_ResultValid   : out std_logic;
        O_Result        : out std_logic_vector(G_GenericA+G_GenericB-1 downto 0)
    );
end component;

constant CST_GENERIC_A  : integer := 12;
constant CST_GENERIC_B  : integer := 5;

signal SR_Clock         : std_logic := '0';
signal SR_Reset         : std_logic;
signal SR_Enable        : std_logic;
signal SR_Data          : std_logic_vector(CST_GENERIC_A-1 downto 0);
signal SR_Address       : std_logic_vector(CST_GENERIC_B-1 downto 0);
signal SC_Ready         : std_logic;
signal SC_ResultValid   : std_logic;
signal SC_Result        : std_logic_vector(CST_GENERIC_A+CST_GENERIC_B-1 downto 0);

begin

    SR_Clock <= not SR_Clock after 7 ns;

    SR_Reset <= '1' , '0' after 59 ns , '1' after 2313 ns , '0' after 2350 ns;

    instance1_Module : Module
        generic map(
            G_GenericA  => CST_GENERIC_A    ,
            G_GenericB  => CST_GENERIC_B
        )
        port map(
            I_Clock         => SR_Clock         ,
            I_Reset         => SR_Reset         ,
            I_Enable        => SR_Enable        ,
            I_Data          => SR_Data          ,
            I_Address       => SR_Address       ,
            O_Ready         => SC_Ready         ,
            O_ResultValid   => SC_ResultValid   ,
            O_Result        => SC_Result
        );

    process     -- process de pilotage des entrees du composant a tester
    begin
        SR_Enable   <= '0';
        SR_Data     <= (others => '0');
        SR_Address  <= (others => '0');
        wait for 61 ns;                     -- wait : instruction non synthetisable
        wait until rising_edge(SR_Clock);
        SR_Enable   <= '1';
        SR_Data     <= std_logic_vector(to_unsigned (111 , CST_GENERIC_A));
        SR_Address  <= std_logic_vector(to_unsigned (15 , CST_GENERIC_B));
        wait until rising_edge(SR_Clock);
        SR_Enable   <= '1';
        SR_Data     <= std_logic_vector(to_unsigned (1 , CST_GENERIC_A));
        SR_Address  <= std_logic_vector(to_unsigned (7 , CST_GENERIC_B));

        -- ... --

    end process;

end archi_tb_Module;