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Register⚓

Simple register⚓

Here is one example of a register with synchronous init and enable. Whenever the init input is high and there is a rising edge of the clock, the value stored in the O_S signal will be set to "00000000". When the init is low, the load is high and there is a rising edge of the clock, the O_S signal will be set to the value present in I_D.

Register with asynchronous reset and synchronous enable

Register with **Synchronous** Reset
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architecture archi of Registre is

signal SR_Register : std_logic_vector(7 downto 0) := (others => '0');

begin

  process(I_Clock)
  begin
    if(rising_edge(I_Clock))then
      if(I_init = '1')then
        SR_Register <= (others => '0');
      elsif(I_Load = '1')then
        SR_Register <= I_InputData;
      end if;
    end if;
  end process;

end archi;

A register can be seen as a row of flip-flop, each one storing a bit of the signal (8 bits here).

Shift register⚓

Here is one example of a shift register with a parallel load.

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architecture archi of RegistreDecalage is

  signal SR_Reg : std_logic_vector(7 downto 0);

begin

  process(I_Clock)
  begin
    if(rising_edge(I_Clock))then
      if(I_Enable = '1')then
        if(I_Load = '1')then
          SR_Reg <= I_D;
        else
          SR_Reg(6 downto 0) <= SR_Reg(7 downto 1);
          SR_Reg(7)          <= '0';
        end if;
      end if;
    end if;
  end process;

  O_S <= SR_Reg(0);

end archi;

The shift can be done the same way with arrays.