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Process⚓

Processes in VHDL are used to describe the operation of a part of a circuit, in particular circuits (using a clock) or complex combinatorial circuits. In processes it is possible to use conditional structures such as the classic if/elsif/else and case.

A process has a sensitivity list, i.e. a list of input signals. The process reacts to the changes of state of the signals that are present in the sensitivity list. It is crucial to fill in this sensitivity list correctly.

On the other hand, a signal that is only updated in the process does not need to be present in the sensitivity list.

Synchronous process⚓

A synchronous process has, as its name indicates, an operation synchronized by the events affecting a signal in its sensitivity list. We call this signal the clock, and most often processes of this type are synchronized on the rising edge of the clock, i.e. the passage from state 0 to state 1. The process updates the signals that it controls only at the time of the rising edge, whatever the evolution of the signals used in this process. For this reason, the sensitivity list of a synchronous process is a bit special. It contains only the clock and possibly a reset in the case of an asynchronous reset. Even if signals are read or used in the synchronous part, it is not necessary to put them in the sensitivity list.

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process(I_Clock)  -- sensitivity list in brackets, consisting of a clock and eventually a reset
begin

  if(rising_edge(I_Clock)) then
    if I_Reset = '1' then   -- active high synchronous reset
        -- what happens if the reset is active
    else
        -- what happens at the time of a clock rising edge without reset
    end if;
  end if;
end process;

Is the asynchronous reset mandatory ?

The asynchronous reset is often present in VHDL synchronous process. But in some if not most FPGA designs, it is vastly optionnal. Its presence might even be a nuisance. A really good overview of the question is presented here Get your Priorities Right — Make your Design Up to 50% Smaller https://www.xilinx.com/support/documentation/white_papers/wp275.pdf

Asynchronous process⚓

The asynchronous process, being by definition combinatorial, must react immediately to the change of state of any of its input signals. It is therefore imperative to fill in the sensitivity list exhaustively.

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process(S1,S2,S3,S3,S5,S6)
begin
  -- description of the circuit using the signals in the sensitivity list. For example :
  if(S1 = '1')then
    S7 <= S5 xor S6; -- S7 does not have to be in the sensitivity list, it is not read
  elsif(S2 = '1')then
    S7 <= S3;
  else
    S7 <= S4;
  end if;
end process;

Implicit process⚓

It is possible to describe the operation of a circuit outside an explicit process. This is called an implicit process. Implicit processes are used when it is not necessary to use a process as such. Putting a permanent connection (assignment) between two signals in an explicit process is of no interest, it is done outside:

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process(...)
begin
    ...
end process;

A <= B and C;  -- Implicit process here

process(...)
begin
    ...
end process;