Component Instantiation
To create a component, it is often very interesting to split it into sub-components. Once the subcomponents have been created and tested, they must be assembled. The use of a sub-component in the current component is called an instantiation, we can use one or multiple instances of a sub-component. Once the sub-components are instantiated, they must be connected to the inputs/outputs/signals of the current component. In this case we speak of structural description.
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116 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Comp1 is
generic(
G_SizeInput : natural;
G_SizeS1 : natural;
G_SizeS2 : natural;
G_SizeS3 : natural);
port(
I_Clock : in std_logic;
I_E1 : in std_logic_vector(G_SizeInput-1 downto 0);
I_E2 : in std_logic_vector(G_SizeInput-1 downto 0);
I_Control : in std_logic;
O_S1 : out std_logic_vector(G_SizeS1-1 downto 0);
O_S2 : out std_logic_vector(G_SizeS2-1 downto 0);
O_S3 : out std_logic_vector(G_SizeS3-1 downto 0);
O_S4 : out std_logic_vector(G_SizeS3-1 downto 0);
O_S5 : out std_logic_vector(G_SizeS1-1 downto 0);
O_S6 : out std_logic_vector(G_SizeS2-1 downto 0));
end entity Comp1;
architecture archi_Comp1 of Comp1 is
component CompA is
generic(
G_Data : natural;
G_Out : natural);
port(
I_Clock : in std_logic;
I_Data1 : in std_logic_vector(G_Data-1 downto 0);
I_Data2 : in std_logic_vector(G_Data-1 downto 0);
I_Control1 : in std_logic;
I_Control2 : in std_logic;
O_Control : out std_logic;
O_Data1 : out std_logic_vector(G_Out-1 downto 0);
O_Data2 : out std_logic_vector(G_Out-1 downto 0));
end component;
component CompW is
generic(
G_X1 : natural;
G_X3 : natural;
G_Y1 : natural;
G_Y2 : natural);
port(
I_X1 : in std_logic_vector(G_X1-1 downto 0);
I_X2 : in std_logic;
I_X3 : in std_logic_vector(G_X3-1 downto 0);
O_Z1 : out std_logic;
O_Y1 : out std_logic_vector(G_Y1-1 downto 0);
O_Y2 : out std_logic_vector(G_Y2 downto 0));
end component;
signal SC_Z1_1 : std_logic;
signal SC_Z1_2 : std_logic;
signal SC_Data1 : std_logic_vector(G_SizeS3-1 downto 0);
signal SC_Data2 : std_logic_vector(G_SizeS3-1 downto 0);
signal SC_X1 : std_logic;
begin
A : CompA
generic map (
G_Data => G_SizeInput,
G_Out => G_SizeS3)
port map (
I_Clock => I_Clock,
I_Data1 => I_E1,
I_Data2 => I_E2,
I_Control1 => SC_Z1_1,
I_Control2 => SC_Z1_2,
O_Control => SC_X1,
O_Data1 => SC_Data1,
O_Data2 => SC_Data2);
W1 : CompW
generic map (
G_X1 => G_SizeInput,
G_X3 => G_SizeS3,
G_Y1 => G_SizeS1,
G_Y2 => G_SizeS2)
port map (
I_X1 => I_E1,
I_X2 => SC_X1,
I_X3 => SC_Data1,
O_Z1 => SC_Z1_1,
O_Y1 => O_S1,
O_Y2 => O_S2);
W2 : CompW
generic map (
G_X1 => G_SizeInput,
G_X3 => G_SizeS3,
G_Y1 => G_SizeS1,
G_Y2 => G_SizeS2)
port map (
I_X1 => I_E1,
I_X2 => SC_X1,
I_X3 => SC_Data2,
O_Z1 => SC_Z1_2,
O_Y1 => O_S5,
O_Y2 => O_S6);
-- Il est possible d'ajouter des process autour de ces instanciations
-- pour manipuler des signaux internes si besoin
--process(...)
--begin
-- .
-- .
-- .
--end process;
end architecture;
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