Counters
Example of a modulo 112 counter with synchronous init, enable and load.
Using unsigned type
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26 | architecture archi_Counter of Counter is
signal SR_Counter : unsigned(7 downto 0) := (others := '0');
begin
process (I_Clock) is
begin
if(rising_edge(I_Clock))then
if(I_Init = '1')then
SR_Counter <= (others => '0');
elsif(I_Enable = '1')then
if(I_Load = '1')then
SR_Counter <= unsigned(I_DLoad);
elsif(SR_Counter >= to_unsigned(111 ,8))then
SR_Counter <= (others => '0');
else
SR_Counter <= SR_Counter + 1;
end if;
end if;
end if;
end process;
O_Count <= std_logic_vector(SR_Counter);
end architecture archi_Counter;
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Using integer type:
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26 | architecture archi_Counter of Counter is
signal SR_Counter : integer range 0 to 111 := 0;
begin
process (I_Clock)
begin
if (rising_edge(I_Clock))then
if(I_Init = '1')then
SR_Counter <= 0;
elsif(I_Enable = '1')then
if(I_Load = '1')then
SR_Counter <= to_integer(unsigned(I_DLoad));
elsif(SR_Counter >= 111)then
SR_Counter <= 0;
else
SR_Counter <= SR_Counter + 1;
end if;
end if;
end if;
end process;
O_Count <= std_logic_vector(to_unsigned(SR_Counter , 8));
end architecture archi_Counter;
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