The use of Asynchronous Reset on FPGA

The design for FPGA is based on the same principles as for ASIC. However, because of the difference between these two types of circuits, optimizations are possible in FPGA design. This is the case for the use of an asynchronous reset on the flip-flops. Where it is almost mandatory on an ASIC, it is suboptional in FPGA, and often we can do without it from a functional point of view. This allows to limit the use of resources (LUT) and thus to improve the performances (resources used, consumption, maximum achievable frequency...).

When configuring an FPGA with a bitstream, all its elements can be initialized. So the interest of an asynchronous global reset, whose main goal on an ASIC is to start the design in a known state by initializing all the memory points, is limited on FPGA.

This document explain the caveat of using an asynchronous reset on Xilinx FPGA : https://www.xilinx.com/support/documentation/white_papers/wp275.pdf