Design of a digital synthesizer

Objective

Your mission is to wire correctly all the building blocks of a digital synthesizer running on a digital circuit and then to play the famous "Funkytown" melody (by Lipps Inc.) with the keyboard. The best player will be elected at the end of the lab.

The digital processing core is a reconfigurable Field-Programmable Gate Array (FPGA), an Artix 7 by AMD, associated to peripherals on a board, the Digilent Nexys Video board, as illustrated on the figure below

This lab offers a brief introduction to the design of digital integrated circuits with simple blocks to analyse and then to interconnect. Once wired, all the blocks process samples so that tones can be generated with orders coming from a USB keyboard.

Starting from blocks described in VHDL (a language dedicated to electronics), you will have to

1. analyse time diagrams of blocks to deduce their functions,
2. wire all the blocks together, by completing a VHDL file (wave_generator.vhd), based on your analysis of the time diagrams,
3. perform its synthesis,
4. test the resulting circuit on an FPGA by playing some tones.

Here is the block diagram of the circuit to design.

Note

To synthesize tones, you can use visit this webpage.

You can see that tones are associated to oscillation frequencies of different waveforms: sine, square, triangle or saw-tooth. You will play similar tones but with a light FPGA system (consuming a few Watts, and not dozens/hundreds as a PC would do).

Info

For your information, know that FPGAs have held an essential place in high-end audiophile systems (such as those from PSaudio) for several years and are beginning to break into "consumer" products with high-resolution formats that FPGAs can fully exploit (as in the Chord Mojo for audiophile players). If you are curious, have a look at this video.

Some useful documentation

You will use the Xilinx Vivado software to describe and synthesize your circuit based on the files available on the git repository.

The circuit to be configured is a Xilinx Artix 7 FPGA which is integrated on the Digilent Nexys Video board. The documentation of the board is available here.

This documentation is useful to understand the use of the peripherals.

gitlab repository

A gitlab repository tp-synthe-etudiant is available in your gitlab space on https://gitlab-df.imt-atlantique.fr, in the group corresponding to the course followed. To manipulate it (clone, add, commit, push, pull), please refer to the page Git and Gitlab .

If no repository creation is planned for your course, or if you want to do this lab freely. The reference repository is here: https://gitlab.imt-atlantique.fr/tp-vhdl/tp-synthe-etudiant

Retrieving the gitlab project on https://gitlab-df.imt-atlantique.fr

A git repository has been created for each student on the school's DFVS gitlab instance https://gitlab-df.imt-atlantique.fr. It contains the VHDL sources necessary for the project, scripts to manage the Vivado project, and a compte-rendu.md file to answer the questions. If you work in pairs, choose one of the two, and add your colleague as an owner on the project in gitlab.

First, open a terminal: Ctrl+Alt+T

• Create a directory for the UE Électronique and move into it:

Warning

Remember to adapt the path of the command below to your own needs

mkdir -p ~/path/wish/tp-vhdl-mee/UE-name/
cd !$

• Clone the git repository locally

Warning

Remember to adapt the link of the command below according to the repository on gitlab

git clone https://gitlab-df.imt-atlantique.fr/tp-vhdl-mee/elec_eng/gr-vhdl-$USER/tp-synthe-etudiant-$USER.git

The git clone command allows you to retrieve the entire git repository with its history of modifications.

You can easily see that this command has allowed you to download with the ls -alsh command in the tp-filtre-etudiant-$USER directory.

Digital circuit design

Create a Vivado project

Warning

Never put spaces, accents or special characters in file or directory names! This is true in general, on Windows as well as on Linux. And it crashes Vivado in our case here.

Return to the user's home directory and launch Vivado

To launch vivado on a TP campux machine, open a terminal and run the following commands:

SETUP MEE_VIVADO_CLASSROOM # sets up the environment (license, PATH)

vivado

─ ◻ ✕

Terminal

 

The launch of the tool can be quite long.

A TCL script is provided to automate the project creation. To use it, you need to:

• go to the Tcl console of Vivado, at the bottom of the window.
• go to the proj directory with the cd command: cd tp-synthe-etudiant-$USER/proj (here you have to manually replace $USER with your login)
• type the command source ./create_project.tcl

Warning

There should be no accents, spaces or special characters in the path and file name

Note

shell commands cd, ls, pwd are usable in this console

This will create a complete project that will be deployed on FPGA.

Run and analyse digital circuit simulations

Once the project has been created by the tcl script, you will have this with Vivado:

Then, you can see that a file has syntax errors. Double-click on Syntax Error Files (1) and wave_generator.vhd to open this file. You should see where the errors are : wires ("signals") are missing to interconnect the blocks of the circuit.

Warning

We want you to

1. run simulations to identify the function provided by each module,
2. edit the drawio file that you have in your doc folder and fill in the description of each module, with the tool https://app.diagrams.net/. Then update the png file by exporting the diagram .drawio previously updated.
3. interconnect all the modules in wave_generator.vhd, but only once you have understood the role of each module.

The circuit described in wave_generator.vhd is made up of many modules set up in a hierarchical way as illustrated below.

Module A is provided and already interconnected. It is a finite state machine that will control all the chain by repeating continuously the same sequence to generate periodic waveforms. It is part of the circuit hierarchy that you can browse in Sources .

In the Design Sources, open AudioProc > synthe > tone0 : tone_generator > gen_wave[0].wave_generator_inst > A_inst : module_A. This will open a file: module_A.vhd .

Read it quickly : il will give you a first idea of the control sequence! If you understand everything, you can stop there and register for TAF SEH. Otherwise, continue this lab with the next step.

First simulation : module_B_tb.vhd

In the Sources, select Simulation Sources > sim_1 > module_B_tb(behavior). Right-click on it, select Set as Top in the pop-up menu. Then, module_B_tb will be the simulation file used to run the simulation.

To run the simulation, in the Flow Navigator on the left, click on SIMULATION > Run Simulation > Run Behavioral Simulation.

Once the simulation is executed, you can check the time diagram. Click on Zoom fit.

You can then zoom on different parts of the time diagram to understand the function provided by module B.

Then, in the doc part, open the drawio diagram and annotate it with the type of the module (combinatorial or sequential module?) and the function that you deduced from your analysis of the time diagram.

Next simulations : do the same with modules C, D and E

Modules C, D and E are very similar.

When you check the time diagram, change the waveform style to understand the values provided on the output.

Next simulations : do the same with modules F and H

Modules F and H are similar. What is the difference?

Simulation of module G

A hint : signed integers are coded with 2's complement format.

Simulation of module I

The last module to identify !

Describe the architecture of the wave generator

Once you have understood the role of each module, interconnect them so that you respect the architecture illustrated in the previous figure.

To do that, edit wave_generator.vhd and put the appropriate signal for each input/output of the modules. Refer to the previous architecture !.

Synthesize the circuit for FPGA implementation

You vill run the "hardware compiler" by clicking, in the Flow Navigator on the left, on SYNTHESIS > Run Synthesis.

If you are curious and want to know more on digital circuits, you can explore the syntesized circuit by clicking on SYNTHESIS > Open Synthesized Design > Schematic. Otherwise, skip this!

Test on FPGA

To transfer your architecture to the FPGA, you need to produce a configuration file that corresponds to the circuit that you designed. To do so, you have to generate a bitstream. Click, in the Navigator Flow, on PROGRAM AND DEBUG > Generate Bitstream

This part of the process requires a few minutes. Don't sleep or switch to your favorite hobbies, but ask for a Nexys Video Board !

When the following window pops up, the bitstream is ready! Click on Open Hardware Manager and OK !

Connect your board to :

• the headphones
• the AC/DC adapter (plug it also!)
• the USB keyboard
• the USB port of your computer to transfer the bitstream (use the micro-USB port at the bottom : PROG ! )

Switch power ON (below the power port, on the left top corner).

Then, go back to Vivado and click on Hardware Manager > Open Target > Autoconnect

Then, click on Hardware Manager > Program Device and then on the Program blue button.

You have a Digital Synthesizer !

So now, let's play MUSIC! tones!

4 types of waveform can be played with switches sw1 and sw0: sine (00), square (01), triangle (10), saw-tooth (11).

Keys A Z E R T are used to play 5 tones:

• A = Sol : 392 Hz
• Z = Si-b : 466 Hz
• E = Do : 523 Hz
• R = Mi : 659 Hz
• T = Fa : 698 Hz

You can play the famous part of "Funky town" by Lipps Inc. Do your best!

Do Do Si-b Do Sol Sol Do Fa Mi Do

E E Z E A A E T R E

You can combine up to 4 harmonics with the fundamental tone thanks to switches sw2 to sw5.