Component Instantiation
To create a component, it is often very interesting to split it into sub-components. Once the subcomponents have been created and tested, they must be assembled. The use of a sub-component in the current component is called an instantiation, we can use one or multiple instances of a sub-component. Once the sub-components are instantiated, they must be connected to the inputs/outputs/signals of the current component. In this case we speak of structural description.
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81 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity processing_unit is
generic(
G_dataSize : natural
)
port(
I_clk : in std_logic; -- not explicitely on schematic
I_start : in std_logic;
I_data1 : in std_logic_vector(G_dataSize-1 downto 0);
I_data2 : in std_logic_vector(G_dataSize-1 downto 0);
O_ready : out std_logic;
O_done : out std_logic;
O_result : out std_logic_vector(G_dataSize-1 downto 0)
);
end entity processing_unit;
architecture archi_Comp1 of Comp1 is
component control_unit is
port(
I_clk : in std_logic;
I_startProcessing : in std_logic;
I_processingDone : in std_logic;
O_initProcessing : out std_logic;
O_enableProcessing : out std_logic;
O_ready : out std_logic;
O_done : out std_logic
);
end component;
component arithmetic_unit is
generic(
G_size : natural
);
port(
I_clk : in std_logic;
I_initProcessing : in std_logic;
I_enableProcessing : in std_logic;
I_operand1 : in std_logic_vector(G_size-1 downto 0);
I_operand2 : in std_logic_vector(G_size-1 downto 0);
O_done : out std_logic;
O_dataOut : out std_logic_vector(G_size-1 downto 0)
);
end component;
signal SC_enable : std_logic;
signal SC_init : std_logic;
signal SC_done : std_logic_vector(G_SizeS3-1 downto 0);
signal SC_Data2 : std_logic_vector(G_SizeS3-1 downto 0);
signal SC_X1 : std_logic;
begin
control_unit_2: entity work.control_unit
port map (
I_clk => I_clk,
I_startProcessing => I_start,
I_processingDone => SC_done,
O_initProcessing => SC_init,
O_enableProcessing => SC_enable,
O_ready => O_ready,
O_done => O_done
);
arithmetic_unit_1: entity work.arithmetic_unit
generic map (
G_size => G_dataSize)
port map (
I_clk => I_clk,
I_initProcessing => SC_init,
I_enableProcessing => SC_enable,
I_operand1 => I_data1,
I_operand2 => I_data2,
O_done => SC_done,
O_dataOut => O_result
);
end architecture;
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